Method of fabricating circuit board

ABSTRACT

A method of fabricating a circuit board including at least one insulation layer and at least one wiring layer, the method including a first step of forming a wiring trench in a surface of the insulation layer, a second step of forming a conductor layer serving as the wiring layer in the wiring trench such that at least a portion of the conductor layer is embedded in the wiring trench, and a third step of cutting a surface of the conductor layer with a cutting tool to form the wiring layer.

BACKGROUND OF THE INVENTION

The present invention relates to a method of fabricating a circuit board, and particularly, relates to a method of fabricating a circuit board in which a wiring trench is formed in an insulation layer and a conductor layer is formed in the wiring trench.

A method of fabricating a circuit board, for instance, a semi-additive process has been conventionally known. In the semi-additive process, a laminate formed by laminating an insulating film made of a resin material which contains an epoxy resin as a main component on a core substrate is pressed under heating using a vacuum compression-bonding hot press so that the insulating resin film is bonded to the core substrate while being heat-cured. Subsequently, via holes are formed in the insulating resin film by laser irradiation or the like. Then, an electroless plating layer is formed on the insulating resin film so as to cover an inner peripheral wall thereof which defines the respective via holes. After that, a plating resist layer of a desired shape is formed on the electroless plating layer, and the electroless plating layer with the plating resist layer as a mask is subjected to electroplating to thereby obtain a wiring pattern having a desired shape.

However, in recent years, there is an increasing tendency toward a fine structure of the wiring pattern, so that it becomes difficult to comply with the fine structure thereof by the above-described semi-additive process. In the semi-additive process, the wiring pattern is formed on the insulating resin film, and only an underside of the wiring is contacted with the insulating resin film. Therefore, as the wiring pattern becomes finer, the contact area of the wiring with the insulating resin film is reduced to thereby cause deterioration in bonding strength thereto so that the wiring tends to be peeled off during the fabricating process. Further, as the wiring pattern becomes finer, the contact area of the plating resist layer with the insulating resin film is also reduced to thereby cause deterioration in bonding strength thereto and peel-off of the plating resist layer during the fabricating process.

In order to solve the above problems, there has been proposed formation of the wiring by a damascene process (or a so-called trench filling process). Japanese Patent Application Unexamined Publication No. 2008-085373 discloses a damascene process in which a wiring trench having a desired shape is formed on an insulating resin film by photolithography and etching, and a conductor layer is formed in the wiring trench and on a surface of the insulating resin film by plating. After that, the surface of the insulating resin film is polished by chemical mechanical polishing (CMP) to remove a surplus of a material of the conductor layer except for a portion thereof located within the wiring trench.

As described above, in the damascene process, since wiring is formed in the wiring trench, an underside of the wiring and both side surfaces thereof are contacted with an inside wall of the wiring trench formed on the insulating resin film, that is, the wiring is formed in such a state as embedded in the wiring trench. Therefore, it is possible to reduce a fear of peeling off the wiring or the plating resist layer during the fabricating process.

SUMMARY OF THE INVENTION

As explained above, the damascene process can satisfy the formation of a fine structure of the wiring pattern. However, a configuration of the surface polished by CMP is influenced by that of the surface before being subjected to polishing by CMP. Therefore, there is generated a local area of the conductor layer which is excessively polished, or there is contrarily generated is polished in an insufficient degree. Further, even in a case where a surplus of the conductor layer is removed by another process except for CMP, for instance, wet etching, a thickness of the conductor layer formed by plating also tends to become non-uniform to thereby cause the same problems as described above.

In a case where a local area of the conductor layer is excessively polished, a thickness of the wiring formed in the local area becomes smaller so that there will occur a problem that specified current cannot be flowed in the wiring. On the other hand, in a case where a region of the conductor layer is polished in an insufficient degree, there will occur a problem that a short circuit is caused between adjacent portions of the wiring in the region of the conductor layer due to lack of polishing.

The present invention was made in view of the above problems. It is an object of the present invention to provide a method of fabricating a circuit board which is capable of suppressing excessive cutting or lack of cutting of a conductor layer to serve as a wiring layer.

In one aspect of the present invention, there is provided a method of fabricating a circuit board including at least one insulation layer and at least one wiring layer, the method including:

-   -   a first step of forming a wiring trench in a surface of the         insulation layer;     -   a second step of forming a conductor layer serving as the wiring         layer in the wiring trench such that at least a portion of the         conductor layer is embedded in the wiring trench; and     -   a third step of cutting a surface of the conductor layer with a         cutting tool to form the wiring layer.

In the method of fabricating a circuit board according to the first aspect of the present invention, the conductor layer to serve as the wiring layer is formed such that at least a portion of the conductor layer is embedded in the wiring trench formed in the insulation layer, and a surface of the conductor layer formed is cut with a cutting tool. Accordingly, when the surface of the conductor layer is cut, a configuration of the cut surface of the conductor layer can be less influenced by a configuration (for instance, concave portions and convex portions) of the insulation layer and the conductor layer, so that lack of cutting or excessive cutting of the conductor layer can be suppressed. Further, since the surface of the conductor layer is treated by the cutting work, it is possible to reduce roll-off in a metal material of the conductor layer which will occur during the polishing work. Further, since a configuration of the cut surface of the conductor layer can be less influenced by a configuration (for instance, concave portions and convex portions) of the insulation layer and the conductor layer, the cut surface of the conductor layer can be flat in shape. Therefore, even in a case where a laminated structure is formed by a plurality of insulation layers and a plurality of wiring layers, a surface of the circuit board can be formed into a flat shape to thereby suppress occurrence of defocus upon being exposed to light.

Further, a diamond bite can be used as the cutting tool. The diamond bite has a remarkably high wear resistance, and therefore, the diamond bite can be used for a long period of time. Further, a surface roughness of the conductor layer which is obtained when the cutting work is finished is low, thereby reducing concave portions and convex portions which are generated on the surface of the wiring layer. As a result, it is possible to reduce electric noise that is generated in the wiring layer. Furthermore, the diamond bite has a high hardness, thereby conducting the cutting work at high speed and enhancing productivity.

Further, in a further aspect of the present invention, there is provided the method of fabricating a circuit board, wherein in the third step, the surface of the conductor layer as well as the surface of the insulation layer are cut to form a roughened surface on the insulation layer. By forming the roughened surface on the insulation layer, adhesion of the insulation layer to the insulation layer to be laminated on the cut surface (i.e., the roughened surface) of the insulation layer can be enhanced. Further, since the surface of the insulation layer is cut, it is not necessary to remove the wiring material adhered to the surface of the insulation layer when the wiring layer is formed. As a result, the fabricating process of the circuit board can be simplified.

Further, in a still further aspect of the present invention, there is provided the method of fabricating a circuit board, wherein in the third step, the cutting operation is repeatedly carried out plural times in a plurality of stages. By carrying out the cutting operation plural times in the plurality of stages, it is possible to perform the cutting work with a high accuracy. Further, even in a case where the conductor layer has a large thickness, the conductor layer can be well subjected to cutting.

Furthermore, in a still further aspect of the present invention, there is provided the method of fabricating a circuit board, wherein the second step includes a step of forming a first conductor layer in the wiring trench by electroless plating, and a step of forming a second conductor layer on the first conductor layer by electroplating. By previously subjecting the insulation layer to electroless plating, the conductive layer can be formed by electroplating with a high film forming speed. As a result, productivity of the circuit board can be enhanced.

The method of fabricating a circuit board according to the present invention can attain an effect of suppressing excessive cutting and lack of cutting of a conductor layer that serves as a wiring layer.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a sectional view of a circuit board fabricated by a method of fabricating a circuit board according to an embodiment of the present invention.

FIGS. 2A and 2B are diagrams showing a core substrate forming step of the method of fabricating a circuit board according to the embodiment of the present invention.

FIGS. 3A, 3B, 4A, 4B, 5A and 5B are diagrams showing a build-up step of the method of fabricating a circuit board according to the embodiment of the present invention.

FIG. 6 is a diagram showing a solder resist layer forming step of the method of fabricating a circuit board according to the embodiment of the present invention.

FIG. 7 is a diagram showing a back-end forming step of the method of fabricating the circuit board according to the embodiment of the present invention.

FIGS. 8A, 8B and 8C are diagrams showing examples of a conductor layer polished by chemical mechanical polishing (CMP).

FIG. 9 is a SEM image of a cut surface obtained in the build-up step of the method of fabricating the circuit board according to the embodiment.

DETAILED DESCRIPTION OF THE INVENTION

In the following, an embodiment of the present invention is explained in detail by referring to the accompanying drawings. In this embodiment, a circuit board includes a build-up layer formed on a core substrate. However, the circuit board is not limited to that in this embodiment, and may be a circuit board having no core substrate. For ease of understanding, directional terms such as “upper”, “lower”, etc. are used in the following description, but merely denote directions as viewed in the drawings.

FIG. 1 is a sectional view of a circuit board 1 according to the embodiment. As shown in FIG. 1, the circuit board 1 includes a core substrate 2, a build-up layer 3 formed on an upper surface of the core substrate 2 (i.e., on an upper surface side of the circuit board 1), a build-up layer 13 formed on a lower surface of the core substrate 2 (i.e., on a lower surface side of the circuit board 1), a solder resist layer 4 formed on a surface of the build-up layer 3 (i.e., on the upper surface side of the circuit board 1), a solder resist layer 14 formed on a surface of the build-up layer 13 (i.e., on the lower surface side of the circuit board 1), a solder bump 5 formed on a surface of a connecting terminal T1 of the build-up layer 3 (i.e., on the upper surface side of the circuit board 1), and a solder ball 15 formed on a surface of a connecting terminal T11 of the build-up layer 13 (i.e., on the lower surface side of the circuit board 1).

The core substrate 2 is a plate-like resin substrate that may be in the form of a heat-resistant resin plate (for instance, a bismaleimide-triazine resin plate), a fiber reinforced resin plate (for instance, a glass fiber reinforced epoxy resin plate) or the like. Core conductor layers 21, 22 which serve as metal wiring layers L1, L11 are respectively formed on the upper and lower surfaces of the core substrate 2. The core substrate 2 is provided with a plurality of through holes 23 formed by drilling or the like. Formed in an inner peripheral wall surface which defines the respective through holes 23 is a through-hole conductor 24 which electrically connects the core conductor layers 21, 22 with each other. The through hole 23 is filled with a resin filler 25 made of such as an epoxy resin.

(Construction of Upper Surface Side)

The build-up layer 3 is constituted of resin insulation layers 31, 33 laminated on the side of the upper surface of the core substrate 2, and wiring layers 32, 34 formed on the resin insulation layers 31, 33, respectively. The resin insulation layer 31 is made of a thermosetting resin composition. The resin insulation layer 31 is provided with wiring trenches 31 a and via holes 31 b which are formed into desired shapes, respectively. A wiring layer 32 serving as metal wiring layer L2 is formed in the wiring trenches 31 a by plating. A via conductor 35 which electrically connects the core conductor layer 21 and the wiring layer 32 with each other is formed in the via holes 31 b by plating.

The resin insulation layer 33 is made of a thermosetting resin composition. The resin insulation layer 33 is formed with wiring trenches 33 a and via holes 33 b which are formed into desired shapes, respectively. A wiring layer 34 with the connecting terminal T1 is formed in the respective wiring trenches 33 a by plating. A via conductor 36 which electrically connects the wiring layer 32 and the wiring layer 34 with each other is formed in the respective via holes 33 b by plating. The connecting terminal T1 is a connecting terminal to be connected with, for instance, a semiconductor chip. Further, a nickel (Ni) plating layer is formed on the surface of the connecting terminal T1 by electroless plating, and a gold (Au) plating layer is formed on a surface of the Ni plating layer by electroless plating.

The solder resist layer 4 is formed by laminating a solder resist film on the surface of the build-up layer 3 or applying a liquid solder resist thereto. The solder resist layer 4 is formed with openings 4 a which each serves for partially exposing the surface of the respective connecting terminals T1 to the outside. With the provision of the openings 4 a, a part of the surface of the respective connecting terminals T1 is exposed to the outside through the respective openings 4 a. That is, the respective openings 4 a of the solder resist layer 4 has a solder-mask-defined (SMD) shape to expose a part of the surface of the respective connecting terminals T1 to the outside.

In the respective openings 4 a, a solder bump 5 made of a solder substantially free of Pb such as, for instance, Sn—Ag, Sn—Cu, Sn—Ag—Cu and Sn—Sb is electrically connected with the connecting terminal T1. Meanwhile, in a case where a semiconductor chip and the like are mounted on the upper surface of the circuit board 1, the connecting terminal T1 of the circuit board 1 and the terminal of the semiconductor chip and the like are electrically connected with each other by ref lowing the solder bump 5 of the circuit board 1.

(Construction of Lower Surface Side)

The build-up layer 13 is constituted of resin insulation layers 131, 133 laminated on the side of the lower surface of the core substrate 2, and wiring layers 132, 134 formed on the resin insulation layers 131, 133, respectively. The resin insulation layer 131 is made of a thermosetting resin composition. The resin insulation layer 131 is provided with wiring trenches 131 a and via holes 131 b which are formed into desired shapes, respectively. A wiring layer 132 serving as metal wiring layer L12 is formed in the wiring trenches 131 a by plating. A via conductor 135 which electrically connects the core conductor layer 22 and the wiring layer 132 with each other is formed in the via holes 131 b by plating.

The resin insulation layer 133 is made of a thermosetting resin composition. The resin insulation layer 133 is formed with wiring trenches 133 a and via holes 133 b which are formed into desired shapes, respectively. A wiring layer 134 with the connecting terminal T11 is formed in the respective wiring trenches 133 a by plating. A via conductor 136 which electrically connects the wiring layer 132 and the wiring layer 134 with each other is formed in the respective via holes 133 b by plating. The connecting terminal T11 is a connecting terminal to be connected with, for instance, a mother board, a socket, etc. (hereinafter referred to a mother board, etc.). Further, a nickel (Ni) plating layer is formed on the surface of the connecting terminal T11 by electroless plating, and a gold (Au) plating layer is formed on a surface of the Ni plating layer by electroless plating.

The solder resist layer 14 is formed by laminating a solder resist film on the surface of the build-up layer 13 or applying a liquid solder resist thereto. The solder resist layer 14 is formed with openings 14 a which each serves for partially exposing the surface of the respective connecting terminals T11 to the outside. With the provision of the openings 14 a, a part of the surface of the respective connecting terminals T11 is exposed to the outside through the respective openings 14 a. That is, the respective openings 14 a of the solder resist layer 14 has a SMD shape to expose a part of the surface of the respective connecting terminals T11 to the outside.

In the respective openings 14 a, a solder ball 15 made of a solder substantially free of Pb such as, for instance, Sn—Ag, Sn—Cu, Sn—Ag—Cu and Sn—Sb is electrically connected with the connecting terminal T11. Meanwhile, in a case where a mother board, etc. are mounted on the lower surface of the circuit board 1, the connecting terminal T11 of the circuit board 1 and the terminal of the mother board, etc. are electrically connected with each other by reflowing the solder ball 15 of the circuit board 1.

(Method of Fabricating Circuit Board 1)

FIG. 2A to FIG. 4B are diagrams for explaining a method of fabricating the circuit board 1 as shown in FIG. 1. Referring to FIG. 2A to FIG. 4B, the method of fabricating the circuit board 1 according to the embodiment of the present invention will be explained hereinafter.

(Core Substrate Forming Step: FIG. 2A to FIG. 2B)

A copper-clad laminate is prepared by adhering a copper foil to upper and lower surfaces of a plate-like resin substrate. The copper-clad laminate is subjected to drilling with a drill such that through holes to be used as the through holes 23 are formed in predetermined positions. Then, the copper-clad laminate is successively subjected to electroless copper plating and copper electroplating in a conventionally known manner such that the through-hole conductor 24 is formed on the inner peripheral wall surface of the through holes 23, and a copper plating layer is formed on upper and lower surfaces of the copper-clad laminate (see FIG. 2A).

After that, a resin filler 25 such as an epoxy resin is filled in the through-hole conductor 24. Subsequently, the copper plating layer formed on the copper foil on the upper and lower surfaces of the copper-clad laminate is formed into a desired shape by etching, so that the core conductor layer 21 serving as the metal wiring L1 is formed on the upper surface of the copper-clad laminate, and the core conductor layer 22 serving as the metal wiring L11 is formed on the lower surface of the copper-clad laminate to thereby obtain the core substrate 2 (see FIG. 2B). Meanwhile, it is desirable that after the step of forming the through holes 23, the copper-clad laminate is subjected to desmear treatment to remove a smear remaining in a periphery of the respective through holes of the copper-clad laminate.

(Build-up Step: FIG. 3 to FIG. 5)

Insulating resin films serving as the resin insulation layers 31, 131 are laminated on the upper and lower surfaces of the core substrate 2, respectively. The respective insulating resin films contain an epoxy resin as a main component. The thus obtained laminate is pressed under heating by a vacuum compression-bonding hot press so that the insulating resin films are bonded to the core substrate while being heat-cured. Next, wiring trenches 31 a, 131 a and via holes 31 b, 131 b are formed in the respective resin insulation layers 31, 131 by irradiating the respective insulation layers 31, 131 with a laser using a conventionally known laser processing machine (see FIG. 3A). After the wiring trenches 31 a, 131 a and the via holes 31 b, 131 b are formed, the respective resin insulation layers 31, 131 are subjected to roughening treatment to thereby roughen an inner peripheral surface which defines the respective wiring trenches 31 a, 131 a and an inner peripheral surface which defines the respective via holes 31 b, 131 b. The wiring trenches 31 a, 131 a and the via holes 31 b, 131 b may be formed via exposure to light and development treatment.

Subsequently, an electroless copper plating layer (a first conductor layer) C1 is formed on the surface of the resin insulation layer 31 which includes the inner peripheral surface of the respective wiring trenches 31 a and the inner peripheral surface of the respective via holes 31 b, by electroless plating. The electroless copper plating layer (the first conductor layer) C1 is also formed on the surface of the resin insulation layer 131 which includes the inner peripheral surface of the respective wiring trenches 131 a and the inner peripheral surface of the respective via holes 131 b, by electroless plating. Next, a copper electroplating layer (a second conductor layer) C2 is formed on a surface of the respective electroless copper plating layers C1 by electroplating (see FIG. 3B). Thus, a multilayer conductor constituted of the electroless copper plating layer C1 and the copper electroplating layer C2 is formed on the upper and lower surfaces of the core substrate 2.

Next, a surface of the multilayer conductor constituted of the electroless copper plating layer C1 and the copper electroplating layer C2 is cut with a diamond bite in a thickness direction thereof a plurality of times so as to remove a surplus of each of the electroless copper plating layer C1 and the copper electroplating layer C2 (see FIG. 4A). Thus, the wiring layers 32, 132 and the via conductors 35, 135 are obtained (see FIG. 4B). Meanwhile, in FIG. 4B to FIG. 5B, the electroless copper plating layer C1 and the copper electroplating layer C2 are shown not as individual separate layers but as one multilayer conductor.

In the embodiment shown in FIG. 4A, the cutting operation is carried out three times, that is, in first to third stages. Specifically, as shown in FIG. 4A, the multilayer conductor is cut from the side of the surface thereof by a predetermined thickness such that the surplus of each of the electroless copper plating layer C1 and the copper electroplating layer C2 is removed until a position of a cut surface of the multilayer conductor is stepwise changed from position A1 to position A3. Further, in the third stage of the cutting operation, when the surface of each of the electroless copper plating layer C1 and the copper electroplating layer C2 is cut, the surface of the respective resin insulation layers 31, 131 is also cut to form a roughened surface thereon.

By thus carrying out the cutting operation in a plurality of stages, more precise cutting can be performed. Further, even in a case where a thickness of the respective layers C1, C2 is large, the respective layers C1, C2 can be cut by carrying out the cutting operation in the plurality of stages. Further, by forming the roughened surface on the surface of the respective resin insulation layers 31, 131 in the cutting operation, adhesion of the respective resin insulation layers 31, 131 to the respective resin insulation layers 33, 133 to be laminated on the respective resin insulation layers 31, 131 can be enhanced. Further, since the surface of the respective resin insulation layers 31, 131 is cut, it is possible to omit a step of removing a wiring material (i.e., copper) bonded to the surface of the respective resin insulation layers 31, 131 by etching, and thereby simplify the process of fabricating the circuit board 1. Meanwhile, the cutting operation of the electroless copper plating layer C1 and the copper electroplating layer C2 may be carried out by a commercial cutting machine, for instance, Model Number FS8910 produced by DISCO CORPORATION.

Subsequent to the above-described cutting operation, an insulating film made of a resin material which contains an epoxy resin as a main component and serves as the respective resin insulation layers 33, 133, is laminated on the roughened surface of the respective resin insulation layers 31, 131. Then, thus laminated article is pressed under heating by a vacuum compression-bonding hot press so that the insulating resin film is compression-bonded to the core substrate 2 while being heat-cured. Next, the laminate is subjected to laser irradiation using a conventionally known laser processing machine, so that the wiring trenches 33 a and the via holes 33 b are formed on the resin insulation layer 33, and the wiring trenches 133 a and the via holes 133 b are formed on the resin insulation layer 133 (see FIG. 5A). After the wiring trenches 33 a, 133 a and the via holes 33 b, 133 b are formed, the inner peripheral surface of the respective wiring trenches 33 a, 133 a and the inner peripheral surface of the respective via holes 33 b, 133 b are subjected to roughening treatment. The wiring trenches 33 a, 133 a and the via holes 33 b, 133 b may be formed via exposure to light and development treatment.

Subsequently, plating treatment and cutting operation similarly to the above-described plating treatment and cutting operation for obtaining the wiring layers 32, 132 and the via conductor 35, 135, are carried out. Specifically, an electroless copper plating layer is formed on the surface of the resin insulation layer 33 which includes the inner peripheral surface of the respective wiring trenches 33 a and the inner peripheral surface of the respective via holes 33 b, by electroless plating. The electroless copper plating layer is also formed on the surface of the resin insulation layer 133 which includes the inner peripheral surface of the respective wiring trenches 133 a and the inner peripheral surface of the respective via holes 133 b, by electroless plating. Next, a copper electroplating layer is formed on a surface of the respective electroless copper plating layers by electroplating. After that, the electroless copper plating layers and the copper electroplating layers are cut with a diamond bite to remove a surplus of the electroless copper plating layers and the copper electroplating layers and thereby obtain the wiring layers 34, 134 and the via conductors 36, 136 (see FIG. 5B).

Also in this cutting operation, it is preferable to cut the electroless copper plating layers and the copper electroplating layers in a plurality of stages similarly to the cutting operation for cutting the electroless copper plating layers C1 and the copper electroplating layers C2. Further, it is preferable to cut the surface of the respective resin insulation layers 33, 133 and form a roughened surface thereon. By forming the roughened surface on the respective resin insulation layers 33, 133, it is possible to enhance adhesion of the respective resin insulation layers 33, 133 to the respective solder resist layers 4, 14 which are laminated on the resin insulation layers 33, 133, respectively.

(Solder Resist Layer Forming Step: FIG. 6)

A solder resist film is laminated by pressing on a surface of the build-up layer 3 on which the connecting terminal T1 is provided, and a solder resist film is laminated by pressing on a surface of the build-up layer 13 on which the connecting terminal T11 is provided. The solder resist film laminated on the respective build-up layers 3, 13 is subjected to exposure to light and development treatment so that the solder resist layers 4, 14 respectively having a SMD-shaped openings 4 a, 14 a are obtained. A part of the respective connecting terminals T1, T11 is exposed to an outside through the respective openings 4 a, 14 a. Next, a nickel (Ni) plating layer is formed on the surface of the respective connecting terminals T1, T11 by electroless plating, and a gold (Au) plating layer is formed on a surface of the Ni plating layer by electroless plating.

(Back-End Forming Step: FIG. 7)

Solder paste is applied to the surfaces of the connecting terminals T1, T11 which are respectively exposed to an outside through the openings 4 a, 14 a of the solder resist layers 4, 14, by solder printing. Subsequently, the solder paste is reflowed at a predetermined temperature for a predetermined time, thereby forming the solder bump 5 and the solder ball 15 which are electrically connected with the connecting terminals T1, T11, respectively.

As described above, in the method of fabricating the circuit board 1 according to the embodiment, the copper plating layer (i.e., the conductor layer) which form the respective wiring layers 32, 34, 132, 134 is cut with a diamond bite. Therefore, the cut surface of the copper plating layer can be less influenced by the configuration (for instance, concave portions and convex portions) of a surface of the respective wiring layers 32, 34, 132, 134 and the respective resin insulation layers 31, 33, 131, 133 which are to be subjected to cutting. As a result, it is possible to suppress lack of cutting and excessive cutting of the conductor layer which form the respective wiring layers 32, 34, 132, 134.

In particular, in a case where CMP is carried out to remove the conductor layer formed in the trench having a rectangular bottom region having an area which is not smaller than a size of 7 mm×5 mm when viewed from a direction of a plan view, there tends to frequently occur formation of concave portions on an upper surface of the wiring layer obtained by subjecting the conductor layer to polishing by CMP. The reason therefor is considered as follows. That is, as shown in FIG. 8A, a concave portion 204 tends to be frequently formed on an upper surface of a conductor layer 203 formed in a trench 202 having a rectangular bottom region 201 having an area which is not smaller than a size of 7 mm×5 mm when viewed from the direction of a plan view. In a case where the conductor layer 203 is polished by CMP, a configuration of the upper surface of the conductor layer 203 after being polished by CMP is influenced by that of the conductor layer 203 before being polished by CMP, so that CMP frequently fails to remove the concave portion 204 on the upper surface of the conductor layer 203. Specifically, even though the conductor layer 203 is subjected to CMP, the concave portion 204 may be merely reduced in size, but cannot be removed by CMP. As a result, in a case where CMP is carried out, as shown in FIG. 8B, the concave portion 204 tends to remain on the upper surface of the wiring layer 205 obtained after polishing the conductor layer 203 by CMP. Further, if the bottom region of the trench 202 has an area of at least the above-specified size, the concave portion 204 may remain on the upper surface of the wiring layer 205 after being subjected to CMP even in a case where the bottom region of the trench 202 has any shape (for instance, a circular shape or an oval shape) other than the rectangular shape.

In contrast, in the method of fabricating the circuit board 1 according to the embodiment as described above, when the conductor layer 203 is cut with the diamond bite, a configuration of the cut surface of the conductor layer 203 can be less influenced by a configuration (for instance, concave portions and convex portions) of the upper surface of the conductor layer 203 before being subjected to cutting. For this reason, as shown in FIG. 8C, there can be provided the wiring layer 205 which has substantially no concave portion 204 on the upper surface of the conductor layer 203 even after subjected to cutting. Otherwise, even if any concave portion 204 remains on the upper surface of the wiring layer 205, the concave portion 204 has a depth of 0.5 μm or less.

Further, in the method of fabricating the circuit board 1 according to the embodiment, the cutting work is carried out instead of a polishing work. Therefore, it is possible to suppress occurrence of roll-off which is caused upon polishing the metal material of the conductor layer. Further, since the cut surface of the conductor layer can be less influenced by the configuration of the surface of the respective conductor layers to form the respective wiring layers 32, 34, 132, 134 and the surface of the respective resin insulation layers 31, 33, 131, 133 which are subjected to cutting, the cut surface of the conductor layer is formed into a flat shape. For this reason, even in a case where a plurality of resin insulation layers and a plurality of wiring layers are alternately laminated on each other, the surface of the circuit board can be formed into a flat shape to thereby suppress occurrence of defocus upon being exposed to light.

Further, in the method of fabricating the circuit board 1 according to the embodiment, the diamond bite is used as a cutting tool. Owing to a high durability of the diamond bite, the diamond bite can be used for a long period of time. Further, since a surface roughness of the cut surface is low, it is possible to reduce concave portions and convex portions which are generated on the surface of the respective wiring layers 32, 34, 132, 134. As a result, it is possible to reduce electric noise that is generated in the respective wiring layers 32, 34, 132, 134. In addition, since the diamond bite has a high hardness, the cutting work can be carried out at high speed so that the productivity can be enhanced.

Further, in the method of fabricating the circuit board 1 according to the embodiment, upon cutting the surface of the respective conductor layers which form the respective wiring layers 32, 34, 132, 134, the surface of the respective resin insulation layers 31, 33, 131, 133 is also cut to thereby form a roughened surface on the respective resin insulation layers 31, 33, 131, 133. Owing to formation of the roughened surface, it is possible to enhance adhesion of the respective resin insulation layers 31, 131 to the respective resin insulation layers 33, 133 to be laminated on the respective resin insulation layers 31, 131, and adhesion of the respective resin insulation layers 33, 133 to the respective solder resist layers 4, 14 to be laminated on the respective resin insulation layers 33, 133. Further, since the surface of the respective resin insulation layers 31, 33, 131, 133 is cut, it is not necessary to remove the wiring material (i.e., the copper plating layer) adhered to the surface of the respective resin insulation layers 31, 33, 131, 133 by etching. As a result, the fabricating process of the circuit board 1 can be simplified.

Further, in the method of fabricating the circuit board 1 according to the embodiment, the cutting operation is carried out in multiple stages, so that the cutting work can be performed with a high accuracy. Further, even in a case where the copper plating layer (i.e., the conductor layer) formed by plating has a large thickness, it is possible to cut the copper plating layer. Further, after forming the electroless copper plating layer by electroless plating, the copper electroplating layer is formed by electroplating with a high film forming speed. As a result, the productivity of the circuit board 1 can be enhanced.

EXAMPLE

Next, an example of the method of fabricating the circuit board 1 of the present invention is explained. In the example, in accordance with the fabricating method as described above, a test piece was prepared by forming a copper plating layer embedded in a wiring trench in a resin insulation layer, and then subjecting the copper plating layer to cutting with a diamond bite. A cut surface of the thus obtained test piece was observed by a SEM.

(Preparation of Test Piece)

An insulating film made of a resin material containing an epoxy resin as a main component was laminated on a surface of a plate-like resin substrate as a core substrate to thereby form a laminate. Thus obtained laminate was pressed under heating using a vacuum compression-bonding hot press so that the insulating resin film was compression-bonded to the core substrate while being heat-cured. Next, the laminate was subjected to laser irradiation with a laser processing machine, thereby forming a wiring trench on a surface of the heat-cured insulating resin film. Subsequently, the surface of the insulating resin film was successively subjected to electroless plating and electroplating to thereby form a copper plating layer on the surface of the insulating resin film such that the copper plating layer was formed in the wiring trench and over the remainder of the surface of the insulating resin film. After that, the copper plating layer was cut with a cutting machine “Model Number FS8910” produced by DISCO CORPORATION, so that a wiring layer was formed in the wiring trench. The cutting operation was carried out using a diamond bite.

(Cut Surface of Test Piece)

FIG. 9 is a SEM image of the cut surface of the test piece. As shown in FIG. 9, it was confirmed that the cut surface (particularly, the interface between the copper plating layer X and the insulating resin film Y which were different in material from each other) was in good condition without formation of concave portions and convex portions. Further, it was confirmed that so-called polishing roll-off was not generated on the cut surface.

As described above, it was confirmed that the method of fabricating the circuit board 1 according to the embodiment can provide a cut surface which is less influenced by a configuration (for instance, concave portions and convex portions) of the conductor layer and the resin insulation layer which are to be cut, and is in good condition without formation of concave portions and convex portions.

Other Embodiments

The present invention is not limited to the embodiment as explained above, and may be variously modified without departing from the scope of the present invention. For instance, although in the above embodiment, the circuit board 1 is a ball grid array (BGA) substrate which is connected with a mother board, etc. via the solder balls 15, the circuit board 1 may be a so-called pin grid array (PGA) substrate provided with pins instead of the solder balls 15 or a so-called land grid array (LGA) substrate provided with lands instead of the solder balls 15, and may be connected with the mother board, etc.

Further, in the above embodiment, the shape of the openings of the respective solder resist layers is a so-called solder-mask-defined (SMD) shape. However, the shape of the openings of the respective solder resist layers may be a so-called non-solder-mask-defined (NSMD) shape in which an entire area of the surface of the respective connecting terminals is exposed to an outside through the openings. Furthermore, in the above embodiment, the conductor layer is cut in three stages (that is, three times). However, the number of stages (i.e., the number of execution of the cutting operation) is not limited to three stages, and may be set to an optimal number.

This application is based on prior Japanese Patent Application No. 2011-170245 filed on Aug. 3, 2011 and Japanese Patent Application No. 2012-123031 filed on May 30, 2012. The entire contents of the Japanese Patent Application No. 2011-170245 and the Japanese Patent Application No. 2012-123031 are hereby incorporated by reference.

Further variations of the embodiment and modification as described above will occur to those skilled in the art in light of the above teachings. The scope of the invention is defined with reference to the following claims. 

1. A method of fabricating a circuit board including at least one insulation layer and at least one wiring layer, the method comprising: a first step of forming a wiring trench in a surface of said insulation layer; a second step of forming a conductor layer serving as the wiring layer in said wiring trench such that at least a portion of said conductor layer is embedded in said wiring trench; and a third step of cutting a surface of said conductor layer with a cutting tool to form said wiring layer.
 2. The method as claimed in claim 1, wherein said cutting tool used in said third step is a diamond bite.
 3. The method as claimed in claim 1, wherein in said third step, the surface of said conductor layer as well as the surface of said insulation layer are cut to form a roughened surface on said insulation layer.
 4. The method as claimed in claim 1, wherein in said third step, the cutting operation is carried out plural times in a plurality of stages.
 5. The method as claimed in claim 1, wherein said second step further comprises: a step of forming a first conductor layer in said wiring trench by electroless plating; and a step of forming a second conductor layer on the first conductor layer by electroplating. 